In processor designs using intelligent peripheral devices which take control of the processor memory bus, either on their own or through a separate Direct Memory Access (DMA) controller, in order to transfer data between the peripheral device and the memory, priority is typically given to the peripheral device. Periodically this results in denying the processor access to the memory which causes a loss in processor performance. While a cache based system is able to overcome some of the losses, some will occur when the processor is stalled waiting for instructions or data not yet in the cache. This results in a statistical system performance which is based on the probability of simultaneous conflicting requests. As the bandwidth requirements of the peripheral devices increase, the statistical performance of the processor deteriorates. In systems with hard real-time requirements, such as digital signal processors, system design must assume that there will always be a conflict in order to assure adequate processor performance for the timely completion of real-time tasks.
As long as the processor is operating in the same memory page, access times to retrieve instructions or data are relatively short and deterministic. The program will normally operate within the same memory page with an occasional need to move to a different page. However, when a peripheral device accesses the memory it typically forces the memory to another page. After the peripheral device has completed, the program incurs additional delay in changing back to the original memory page. Short and frequent peripheral device access to the memory can cause additional non-deterministic processor overhead due to the extra access times required for frequent moves from one memory page to another.